1. Field of the Invention
This disclosure relates to a flat panel display device with an oxide thin film transistor and a method of fabricating the same.
2. Discussion of the Related Art
Image display devices used for displaying a variety of information on a screen are one of the core technologies of the information and communication era. Such image display devices have been being developed to be thinner, lighter, and more portable, and furthermore to have a high performance. Actually, flat panel display devices are spotlighted in the display field due to their reduced weight and volume, well known disadvantages of cathode ray tubes (CRTs). Flat panel display devices include OLED (organic light-emitting display) devices, which display images by controlling the light emitting quantity of an organic light emission layer.
The OLED devices are self-illuminating display devices employing a thin light emission layer between electrodes. As such, the OLED devices can become thinner like a paper. Such OLED devices display images by emitting light through an encapsulated substrate. The encapsulated substrate includes a plurality of pixels arranged in a matrix shape and each configured with 3 colored (i.e., red, green and blue) sub-pixels, a cell driver array, and an organic light emission array.
In order to realize a variety of colors, the OLED device employs organic light emission layers, which are configured to emit red, green and blue lights, respectively. The organic light emission layer is interposed between two electrodes and used to form an organic light emission diode.
The OLED device requires a thin film transistor, which can be driven faster. To this end, the OLED device uses an oxide film, such as an IGZO (indium gallium zinc oxide) film, instead of amorphous silicon film a-Si.
FIG. 1 is a cross-sectional view schematically showing a flat panel display device according to the related art.
As shown in FIG. 1, the flat panel display device includes a pixel region 15 configured with a plurality of defined pixel portions and used to display an image, and a data driver 12 disposed in a peripheral area of the pixel region 15. A gate driver is included in the data driver 12 or formed in another peripheral area of the pixel region 15.
The pixel portions within the pixel region 15 are defined gate lines and data lines crossing each other. Also, each of the pixel portions includes thin film transistors formed in such a manner as to be connected to the gate line and the data line.
A plurality of pads is formed on a driver region in which the data driver 12 is disposed. The plurality of pads is used to apply signals to the gate lines and the data lines. The pads are connected to a plurality of line lines. As such, the plurality of link lines are connected to the gate and data lines extended from the pixel region 15.
Particularly, the plurality of link lines are simultaneously formed on a substrate when the gate lines corresponding to low resistance wirings are formed. The data line and the gate line are connected to each other in a pad contact region by means of a connection electrode, because the data line is positioned over the gate line with having an insulation layer therebetween.
FIG. 2 is a data sheet including photographs which illustrate a pin hole fault generated in a pad contact region of the flat panel display device according to the related art. FIG. 3 is a cross-sectional view showing a TFT region within a pixel region and pad contact region taken along a line X-X′ in FIG. 2.
Referring to FIGS. 2 and 3, the thin film transistor formed in a pixel region is configured with a gate electrode 101, an active layer and source/drain electrodes 107a and 107b. The gate electrode 101 is formed on a substrate 100. The active layer includes a channel layer 104 and an ohmic contact layer 105 which are formed over the gate electrode 101 with having a gate insulation film 102 therebetween.
Also, the drain electrode 107b of the thin film transistor formed within the pixel region is connected to a pixel electrode 110 through a contact hole, which is formed in a passivation layer 109.
Meanwhile, a data line 160 within the pad contact region is connected the link line 150, which is formed in an outside of the pixel region 15, by a connection electrode 170. If a fourth mask procedure uses one of a diffraction mask and a half tone mask, an ohmic contact layer pattern 105a and a channel layer pattern 104a remain under the data line 160.
However, as seen from FIGS. 2 and 3, the gate insulation film 102 and the passivation layer are stacked on the link line 150 formed on the substrate 100, and the passivation layer is only formed on the data line 160. As such, etching depths for forming contact holes are different from each other.
Due to this, a pin hole fault can be generated in the data line 160, which covered with only the passivation layer 109, by an over-etch. More specifically, both the gate insulation film 102 and the passivation layer 109 must be etched in order to form a contact hole in the link line 150, which is formed on the substrate 100. On the other hand, when another contact hole is formed in the data line 160 covered with only the passivation layer 109, a pin hole fault by which the gate insulation film 102 under the data line 160 is also etched can be generated in such a manner that another contact hole passes through the data line 160.
Such a pin hole fault damages the data line 160 and the gate insulation film 102. Due to this, a variety of faults including the disconnection of a metal film formed in a contact hole region can be generated.